1. Field of the Invention
This invention relates to a semiconductor memory system and, more particularly, to a semiconductor memory system of the serial column access type.
2. Description of the Related Art
There has been known a semiconductor memory system of the type in which the columns are serially accessed. An example of this type of memory system uses a shift register for the column selection circuits. This will be described referring to FIG. 1. In the figure, reference numerals 51.sub.1 to 51n designate columns (consisting of bit line pairs or data registers), and characters D and D paired data lines. Column selection gates 61.sub.1 to 61n are for connecting columns 51.sub.1 to 51n with the data lines. Column selection circuits 71.sub.1 to 71n are constructed with a shift register. Output signals C1 to Cn are used for two types of signals, column selection signals for enabling column selection gates 61.sub.1 to 61n, and set-up signals for driving the succeeding stages 71.sub.1 to 71n in the shift register in the next access cycle. Input/output drive circuit 81 is for executing the write and read operation of data between paired data lines D and D and input/output pin DQ. Start address set-up circuit 82 is for setting up shift registers 71.sub.1 to 71n in accordance with a start address.
After column select circuit 71.sub.1, for example, is first set up by start address set-up circuit 82, these circuits 71.sub.1 to 71n are successively driven in synchronism with clock pulses for memory system control which are externally and serially applied. In response to a clock pulse, column selection circuit 71.sub.1 is driven, to produce signal C1. The produced signal enables column selection gate 61.sub.1 to set up the connection between column 51.sub.1 and paired data lines D and D. The produced signal C1 further sets up the next stage column selection circuit 71.sub.2 for the next access cycle. In response to the next clock pulse, the next stage column selection circuit 71.sub.2 is driven to produce signal C2. The produced signal C2 enables column selection gate 61.sub.2 to set up the connection between column 51.sub.2 and paired data lines D and D. The produced signal C2 further sets up the next stage column selection circuit 71.sub.3 for the next access cycle. In this way, column selection circuits 71.sub.1 to 71n are enabled in successive order in synchronism with successive clock signals, and consequently columns 51.sub. 1 to 51n are serially accessed.
To cope with problems resulting from a defective column, a redundant column may be used. In the memory system arranged as shown in FIG. 1, however, it is impossible to use the redundant column. The reason for this follows. For example, if column 51.sub.2 is defective, and replaced with a redundant column, defective column 51.sub.2 must be invalidated by disabling column selection gate 61.sub.2. To disable this gate, the shift register including the column selection circuits 71.sub.2 must be stopped in operation. If this shift register operation is stopped, the next stage shift register 71.sub.3 cannot be driven. This indicates that the above serial access of this memory system is impossible.